Reducing Contamination Points in Clean Chemical Delivery from Manufacture to Point of Use

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This paper takes a closer look at ways to more comprehensively meet increasing purity specifications throughout chemical and device manufacturing.


As mega-trends, such as artificial intelligence and robotics, smart homes and smart cars, and the Internet of things evolve to meet growing needs for speed, scale, and reliability, they force integrated circuit (IC) manufacturers to increase processor power efficiency and memory size. At the same time, device manufacturers striving to meet new worldwide consumer and business data demands at lower costs, face significant challenges in terms of process control, yield, and economics.

As logic devices migrate to smaller line widths, 3D NAND architectures increase layers, and DRAM memory density increases, sensitivity to contamination and defects have a greater impact on device performance. To achieve optimum wafer yield and reliability, the microelectronics industry needs to address the increased materials consumption requirements and the material purity challenges for these high-performance technologies from chemical manufacture to their point of use.

Controlling contamination begins with the chemicals that come into direct contact with every wafer. Increasing chemical purity is the first step in enabling process cleanliness and improving device yield. This is why device manufacturers continue to pressure chemical suppliers to deliver a higher level of purity, soon approaching parts per quadrillion (ppq), and avoid introducing contaminants during chemical packaging, transport, and distribution.