Realizing Bottom Line Profits from Wafer Carrier Selection

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INTRODUCTION

The global semiconductor industry is racing to address ever increasing market demands for smaller, more powerful, and technology-laden devices. Market demand for memory, microprocessors, integrated circuit (IC), and system on a chip (SOC) is driving the estimated $463 billion,1,2 industry (for 2018) as more connectivity and intelligence is embedded in all aspects of society. To address this rapidly increasing demand, semiconductor device manufacturers are facing processing challenges to improve yield and density while increasing layers and decreasing device line widths to 10, 7, and 5 nanometers. Controlling key influencers, such as contaminants that include volatile organic compounds (VOC), moisture, and oxygen, provides the opportunity to improve yield in current and future processes.

Semiconductor devices are manufactured using the most automated and technologically advanced processes in the world. From a wafer handling perspective, semiconductor chips begin their journey at the wafer supplier as pure silicon wafers (thin slices of semiconductor material) that have been loaded into Front Opening Shipping Boxes (FOSB) for transportation. Once received at the device manufacturer’s fabrication facility (fab), the wafers are automatically transferred to a Front Opening Unified Pod (FOUP). The wafer will travel 8 to 16 km within the fab as it moves through the hundreds of process steps required to manufacture each microchip. Finally, the finished wafer is transferred to a Horizontal Wafer Shipper (HWS) for secure transport to customers.

This paper looks at the role of front-end to back-end wafer handling carriers, advanced design criteria, and their impact on yields. The primary goal of the wafer carrier is to ensure safe transit, docking, loading/unloading, storage, and movement from point A to point B all while maintaining the cleanliness of the wafer. To assure leading-edge performance in defect protection, it is paramount to understand the contamination challenges in each step of the wafer’s process journey and the benefits of choosing the right partner and products. The choice of wafer carrier expert can play a significant role in improving device yields. For the best results, manufacturers need to partner with a carrier expert who has an in-depth knowledge of material sciences and process control, and a history of design and innovation that can support the entire front-end to back-end device manufacturing process.

Raw materials science is the first key step in addressing and maintaining contamination control. Selecting and sourcing scientifically engineered, custom-compounded polymers with clean carbon loading and extremely low water absorption is a crucial step in reducing contaminants. This will produce wafer carriers with low moisture and low volatile organic absorption and desorption, all while meeting electrostatic discharge requirements. Robust monitoring of the incoming polymers and strict compliance to specifications at every step of the manufacturing process will help assure a consistent and high-quality carrier product. Utilizing manufacturing facilities and processes with stringent adherence to quality standards and to customer process change control requirements provides carriers of the highest quality and assures supply continuity.