Bowling for Contaminants: The New Science of Gas Purification
This white paper explains the importance of applying purification science to managing the gas supply purity from the source throughout all the wafer process steps to ensure the highest device yield.
Purity of gases and chemicals has always played a critical role in the performance and reliability of advanced semiconductors and memory devices. While the fab-cleanroom purity requirements themselves have remained constant, meeting them has become more difficult due to a number of contributing factors. As a result, purity requirements in key process areas in the fab are approaching parts per quadrillion.
To remain competitive, semiconductor manufacturers have increased manufacturing volumes, increasing the overall consumption of gases. Additionally, both logic and advanced memory devices require significantly higher gas consumption per processed wafer to support shrinking geometries and multi-layer device architectures. For example, the move from 20 nm logic to 7 nm logic doubled the number of process steps. As a result, process gas consumption is expected to increase over the next 5 years.
Concurrently, to achieve higher density at lower power, the industry is adopting three dimensional (3D) architectures with finFETS and 3D NAND, which increases the complexity of the processes.
These additional process steps impact yields as there are more opportunities to expose wafers to process excursions. Even trace contaminants in the gas supply can cause measurable shifts that affect chip performance by interacting with a process, potentially costing the manufacturer thousands or even millions of dollars.
As a result of this heightened sensitivity to molecular contamination and increased gas consumption, semiconductor manufacturers are depending on suppliers of both bulk and specialty gases to deliver process gases customized to meet purity requirements. This article explains the importance of applying purification science to managing the gas supply purity from the source throughout all the wafer process steps to ensure the highest device yield.