Precision Engineered Techniques for Coating Plasma Chamber Components

White paper

The continual march toward semiconductor devices that process more information at higher speeds in the most compact footprint possible requires horizontal shrinking of features and vertical stacking of layers. Both these trends require innovative approaches to materials selection and process control to ensure reliability at high-volume production.

Semiconductor processing at advanced nodes involves feature sizes smaller than 10 nanometers (nm), where the presence of even submicroscopic contaminants poses a high risk to device yield. At this scale, every process tool or piece of equipment can be a potential source of contamination, whether it contacts the wafer directly or indirectly. Migration from 2D to 3D structures for high-density memory devices changes the nature of etching and deposition processes, especially as the number of layers for 3D NAND integration grows to 96 and beyond, and new process chemistries become commonplace. As explained in the July 2018 Entegris white paper, 96 Layers and Beyond: Solving 3D NAND Material and Integration Challenges 1, the greater number of lengthy processing steps and high aspect ratio (HAR) features involved place new demands on all steps of the chip manufacturing process, including etching, deposition, and cleaning equipment. Consistent process stability becomes harder to achieve.

The environment inside plasma etch and deposition chambers is just one example of the needs to be kept extremely clean and free of impurities, both to avoid yield loss and to maintain process stability for consistent results from wafer to wafer. Precise control of the process tool component surfaces in the etch chamber is necessary to maintain the desired etch rate and in deposition chambers to maintain the electrical integrity of deposited layers. This paper explains the importance of component coatings for reducing contamination risk and producing higher-yielding semiconductor devices. 

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