EUV Enablement:
Solving Defect Challenges in the EUV Process

The drive for ever more powerful microprocessors and greater memory storage places demands on all steps of the semiconductor wafer fabrication process. At some point, incremental improvements are no longer sufficient, and further device shrinking requires a completely different technology.

The semiconductor industry is now experiencing this with lithography, where extreme ultraviolet (EUV) lithography is replacing 193 nm immersion (193i) lithography for more and more critical chip layers.

Major manufacturers are using EUV lithography for volume production of advanced logic devices now. But even though the technology is in production, there are hurdles to overcome.

Advances in EUV lithography must address three key challenges:

• Reducing contamination from the reticle to control defect levels
• Improving photoresist technology to create a more robust process
• Extending EUV through advances in scanner hardware

This white paper will explain why these advances are necessary for the success and expansion of EUV lithography.