Advanced CMP of Silicon Carbide for EVs and Power ICs
The transition from gas-powered to electric vehicles (EVs) is happening at a faster rate than was predicted a few years ago. Batteries are also operating at higher voltages. Both these trends put pressure on power integrated circuit (IC) manufacturers to produce higher volumes of chips using technologies designed to withstand high-temperature, high-frequency operating environments. Part of the answer lies in transitioning from silicon substrates to silicon carbide (SiC) and gallium nitride (GaN).
Solutions that improve utilization rates of SiC materials and reduce cost of ownership (COO) will be especially valuable. The first steps in fabricating SiC wafers involve grinding, lapping, and polishing the wafers to create the necessary surface properties before depositing active layers. The slurries used to carry out these steps, therefore, are becoming more critical.
Chemical mechanical planarization (CMP) that is optimized for SiC wafers can support greater throughput and higher yield, thereby mitigating the supply chain challenges and reducing COO. This white paper describes challenges specific to CMP of SiC wafers and proposes solutions to improve SiC slurry performance and meet the needs of power IC manufacturers.
This white paper describes challenges specific to chemical mechanical planarization (CMP) of silicon carbide (SiC) wafers and proposes solutions to improve SiC slurry performance and meet the needs of power IC manufacturers.